The present invention generally relates to semiconductor devices and more particularly to a random access memory having a ferroelectric film (FRAM; ferroelectric random access memory) or a miniaturized dynamic random access memory (DRAM) having a high permittivity dielectric film.
With recent advancements in memory technology, particularly with regard to the art of device miniaturization, DRAMs that use a high permittivity dielectric film for the memory cell capacitor are studied intensively. Further, intensive efforts are being made also for FRAMs that use a ferroelectric film for storage of information. An FRAM stores information in the ferroelectric film in the form of polarization and has advantageous features of a non-volatile nature of information storage and a large access speed.
Conventionally, DRAMs are formed to have a dielectric film of SiN or SiO.sub.2 for the capacitor dielectric film of the memory cell capacitor. With an increase of the integration density and a corresponding miniaturization of the device, however, the use of such a conventional dielectric film has caused the problem of insufficient capacitance for the memory cell capacitor due to the excessive miniaturization of the memory cell capacitor. As a DRAM stores information in the memory cell capacitor in the form of electric charges, the decrease of the capacitance of the memory cell capacitor, which occurs inevitably as a result of the device miniaturization, causes a problem of an unreliable read/write operation or an unreliable holding of the stored information.
In order to compensate for such a decrease of the memory cell capacitance, it is proposed to use a high-permittivity dielectric film for the memory cell capacitor of a DRAM. For example, the use of a double oxide film such as (Ba, Sr)TiO.sub.3 (called hereinafter BST) or SrTiO.sub.3 (called hereinafter STO) is studied intensively for this purpose.
Further, it should be noted that a double oxide is used also in FRAMs for a capacitor dielectric film, wherein the double oxide used in a FRAM is a ferroelectric material that shows a spontaneous polarization below a Curie temperature. For example, the use of Pb(Zn, Ti)O.sub.3 (called hereinafter PZT) is studied intensively for the dielectric film of an FRAM.
As these dielectric or ferroelectric films of double oxides have a substantially different nature as compared with a silicon nitride (SiN) film or a silicon oxide (SiO.sub.2) film used conventionally for the capacitor dielectric film of a DRAM, there arises various difficulties when the semiconductor memory device is fabricated to have a conventional structure.
FIG. 1 shows an example of the memory cell of a conventional FRAM that uses a ferroelectric film for the capacitor dielectric film, wherein it should be noted that FIG. 1 shows only the essential part of the device including a local interconnection pattern, while the illustration of interlayer insulation films and interconnection patterns provided further thereon is omitted for the sake of simplicity.
Referring to FIG. 1, the FRAM is constructed on a Si substrate 101 carrying a field oxide film 102, wherein the field oxide film 102 defines a memory cell region on the substrate 101 as usual. Further, the Si substrate 101 carries thereon a gate electrode 104 extending across the memory cell region, wherein a gate insulation film 103 is interposed between the substrate 101 and the gate electrode 104 in the foregoing memory cell region. Further, diffusion regions 105 and 106 are formed at both sides of the gate electrode 104 in the memory cell region as a source and a drain of the memory cell transistor.
The gate electrode 104, on the other hand, is covered by a first interlayer insulation film 107, and a bit line 108 is provided on the interlayer insulation film 107 in electrical contact with the diffusion region 105 via a contact hole formed in the interlayer insulation film 107. The bit line 108 is then covered by a second interlayer insulation film 109, on which a memory cell capacitor is formed.
As indicated in FIG. 1, the memory cell capacitor includes a lower capacitor electrode 110 provided directly on the interlayer insulation film 109, and a capacitor dielectric film 111 is provided on the lower capacitor electrode 110. Further, an upper capacitor electrode 112 is provided on the capacitor dielectric film 111 so as to sandwich the capacitor dielectric film 111 between the lower and upper capacitor electrodes 110 and 112. A third interlayer insulation film 113 further covers the memory cell capacitor thus formed on the second interlayer insulation film 109.
The structure thus formed is provided with a via-hole extending through the interlayer insulation films 107, 109 and 113, and a local interconnection pattern 114 is provided on the interlayer insulation film 113 in electrical contact with the diffusion region 106 exposed by the via-hole and further in electrical contact with the upper capacitor electrode 112, such that the local interconnection pattern 114 connects the diffusion region 106 to the upper capacitor electrode 112 of the memory cell capacitor.
The fabrication of the FRAM of FIG. 1 may be carried out as follows.
First, the Si substrate 101 is formed with the field oxide film 102 such that the field oxide film 102 defines the memory cell region on the substrate 101. Further, a MOS transistor having the gate electrode 104 is formed in the memory cell region as the memory cell transistor of the FRAM, wherein the gate electrode 104 is insulated from the substrate 101 by the gate insulation film 103 and the MOS transistor further includes the diffusion regions 105 and 106 at both sides of the gate electrode 104.
Next, a silicon oxide film is deposited on the structure thus obtained including the gate electrode 104 as the first interlayer insulation film 107, and a contact hole is formed in the interlayer insulation film 107 so as to expose the diffusion region 105 by a well known photolithographic process. After the contact hole is thus formed, a layer of WSi is deposited on the interlayer insulation film 107 including the contact hole such that the WSi layer contacts the exposed diffusion region 105 at the contact hole. By patterning the WSi layer thus formed subsequently, the bit line 108 is obtained.
Next, another silicon oxide film is deposited on the structure thus obtained, to form the second interlayer insulation film 109, and the formation of the lower capacitor electrode 110 is made further on the insulation film 109, wherein the formation of the lower capacitor electrode 110 is made by depositing a Ti film and a Pt film consecutively to form a Pt/Ti structure.
The Pt/Ti film thus formed is then patterned by an ion milling process by using a resist mask to form the lower capacitor electrode 110, and a PZT film is deposited further on the lower capacitor electrode 110 by an RF sputtering process, for example. The PZT film thus deposited is patterned by an ion milling process by using the resist mask to form the capacitor dielectric film 111. Further, a Pt film is deposited on the dielectric film 111, followed by an ion milling process to form the upper capacitor electrode 112, similarly to the lower capacitor electrode 110. Thereby, the memory cell capacitor is formed on the interlayer insulation film 109.
After the memory cell capacitor is formed as such, a silicon oxide film is deposited on the interlayer insulation film 109 as the third interlayer insulation film 113 so as to cover the memory cell capacitor, and the diffusion region 106 is exposed by forming the via-hole noted before, such that the via-hole extends through the interlayer insulation films 107, 109 and 113. Further, a contact hole is formed in the interlayer insulation film 113 to expose the upper capacitor electrode 112, and a conductor layer is deposited on the interlayer insulation film 113 so as to establish an electrical contact with the diffusion region 106 at the via-hole and so as to establish an electrical contact with the upper capacitor electrode 112 at the contact hole of the interlayer insulation film 113. By patterning the conductor layer according to a photolithographic patterning process, one obtains the local interconnection pattern 114.
It should be noted that the conventional FRAM structure of FIG. 1, in which the memory cell capacitor is formed above the field oxide film 102, occupies a large area on the substrate 101 and is thus disadvantageous from a view point of increasing the integration density and hence the storage capacity of the information stored in the FRAM.
In order to eliminate the foregoing shortcoming of the conventional FRAM of FIG. 1 and to increase the integration density thereof further, there is proposed an improved structure of FRAM in FIG. 2, in which the memory cell capacitor is provided immediately above the diffusion region 106. In FIG. 2, it should be noted that those parts explained already are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIG. 2, the FRAM has a structure similar to that of FIG. 1 except that a contact hole is formed through the interlayer insulation films 107 and 109 so as to expose the diffusion region 106, and the lower capacitor electrode 110 of the memory cell capacitor is connected to the diffusion region 106 via a conductive plug 115 of polysilicon or amorphous silicon filling the contact hole. In this construction, the local interconnection pattern 114 is eliminated and the upper capacitor electrode 112 is exposed at the contact hole formed in the third interlayer insulation film 113.
In the FRAM of FIG. 2, the lower capacitor electrode 110 of the memory cell capacitor has preferably a Pt/Ta structure including a stacking of a lower Ta layer and an upper Pt layer, for preventing a diffusion of Si from the conductive plug 115 to the PZT film 111 across the lower capacitor electrode 110. It should be noted that the Si atoms thus penetrated into the PZT film 111 would form an oxide film at the interface between the lower capacitor electrode 110 and the PZT film 111 as a result of a reaction with the oxygen atoms contained in the PZT film 111. By using the foregoing Pt/Ta structure for the lower capacitor electrode 110, the Ta layer acts as an effective diffusion barrier against Si, and the problem of diffusion of Si is successfully eliminated.
In relation to the diffusion barrier, it should be noted that the conventionally used Ti layer is found to be not effective for interrupting the diffusion of Si from the plug 115 to the lower capacitor electrode 110. Further, the use of a Ti layer in the lower capacitor electrode 110 causes the problem of diffusion of Pb and oxygen atoms from the PZT film 111 to the lower capacitor electrode 110 at the time of the RF sputtering process used for forming the PZT film 111. It should be noted that the RF sputter deposition of the PZT film 111 is conducted under an oxidizing atmosphere that contains O.sub.2. A similar problem of oxygen diffusion occurs also when applying an annealing process to the PZT film 111 after a formation thereof. It should be noted that such an annealing process is essential for improving the quality of the PZT film 111 and has to be conducted in an oxidizing atmosphere, while a material such as Pt or Ti does not function as an effective diffusion barrier against oxygen atoms. Thus, the oxygen atoms readily reach the conductive plug 115 underneath the electrode 110 and cause an extensive formation of silicon oxide at the interface between the plug 115 and the electrode 110. When this occurs, there is a substantial risk that the ohmic contact between the electrode 110 and the conductive plug 115 is lost.
Further, the diffusion of Pb from the PZT film 111 across the lower capacitor electrode 110 of the Pt/Ti structure causes a compositional shift in the PZT film 111, and there is a possibility that the PZT film 111 may loose its ferroelectricity or high permittivity, which are essential for the operation of the FRAM. Further, such Pb atoms thus diffused away from the PZT film 111 tend to form PbO at the interface between the Pt layer and the Ti layer in the lower capacitor electrode 110 or at the interface between the electrode 110 and the underlying interlayer insulation film 109. When such a PbO layer is formed, there is a possibility that the film above the PbO layer may scale off.
When forming a BST film for the capacitor dielectric film 111 in place of the PZT film to form a DRAM, on the other hand, a substrate temperature of about 500.degree. C. is required when a sputtering process is employed. When the BST film is formed by a CVD process, on the other hand, a substrate temperature of about 600.degree. C. is required. It should be noted that such a high substrate temperature is required in order to achieve a high permittivity for the deposited BST film. During such a deposition process of the BST film, an oxidizing atmosphere is employed similarly to the case of depositing a PZT film. Thus, there occurs the same problem of diffusion of the oxygen atoms through the lower capacitor electrode 110 when the lower capacitor electrode 110 has the PT/Ti structure. In this case, the formation of a silicon oxide film occurs at the interface between the conductive plug 115 and the lower capacitor electrode 110. Thereby, the ohmic contact to the memory cell capacitor is no longer guaranteed.
When the lower capacitor electrode 110 has the Pt/Ta structure, on the other hand, the diffusion of the oxygen atoms is interrupted effectively at the Ta barrier. However, the use of a Ta barrier causes a problem of formation of Ta.sub.2 O.sub.5 in the lower capacitor electrode 110 at the interface between the Pt layer and the Ta barrier. It should be noted that the Pt layer of the electrode 110 contacting directly the PZT film or the BST film 111 allows a substantially free passage of the oxygen atoms therethrough, and there tends to occur an accumulation of the oxygen atoms thus diffused at the interface between the Ta layer and the Pt layer in the electrode 110.
When such a formation of Ta.sub.2 O.sub.5 occurs in the lower capacitor electrode 110, the memory cell capacitor actually forms a stacked structure in which the Ta barrier layer and the Pt electrode layer sandwich a Ta.sub.2 O.sub.5 layer therebetween, and the BST or PZT film 111 and the upper capacitor electrode layer 112 are stacked consecutively on the Pt electrode layer. Thereby, the memory cell capacitor includes two capacitors connected in series, one including the Ta.sub.2 O.sub.5 layer as the capacitor dielectric film and the other including the BST or the PZT film 111 as the capacitor dielectric film. As Ta.sub.2 O.sub.5 has a permittivity substantially smaller than the permittivity of BST or PZT, the memory cell capacitor having such a series connection structure suffers from the problem of reduced memory cell capacitance. This problem becomes particularly acute when the structure of FIG. 2 is used to form a DRAM.